Introduction to PCB Topology for High Speed Designs

Printed circuit board (PCB) layout topology is critical for high speed electronic designs. As signal speeds and frequencies increase, the physical layout and routing of traces, planes, and components on the PCB becomes increasingly important to maintain signal integrity, minimize crosstalk and electromagnetic interference (EMI), and ensure reliable operation.

Poor PCB topology can lead to a host of issues in high speed designs, including:

• Signal integrity problems like reflections, ringing, and distortion
• Crosstalk between adjacent signals
• Radiated and conducted EMI that can interfere with other circuits or fail EMC regulations
• Power integrity issues and ground bounce
• Compromised reliability and even complete circuit failure

Therefore, it’s essential for PCB designers to understand the principles of good high speed PCB layout topology and follow best practices to create robust boards that meet performance requirements. In this article, we’ll dive into the key aspects of optimizing PCB topology for high speed design.

Signal Integrity Considerations

One of the primary concerns in high speed PCB layout is maintaining good signal integrity (SI). As frequencies increase, formerly short traces start to behave like transmission lines with impedance, delay, and potential for reflections. Some key SI considerations include:

Impedance Control

Maintaining consistent characteristic impedance of traces is critical to prevent reflections caused by impedance discontinuities. This requires careful control of trace width, copper thickness, dielectric height, and dielectric constant (Er).

Target impedances for different technologies include:

Interface	Differential Impedance (Ω)	Single-Ended Impedance (Ω)
USB 2.0	90	–
USB 3.0	90	–
HDMI	100	–
Ethernet	100	–
PCIe	85-100	50-65
DDR2/3 DRAM	–	50-60

Length Matching

For signals that must arrive simultaneously, like clock or bus signals, trace lengths should be tightly matched. The allowable length mismatch depends on the signal rise time. A faster signal requires tighter matching.

As a general rule of thumb:

Allowable mismatch (mils) < 100 * Rise time (ns)

So for a 1 ns rise time signal, traces should be matched within 100 mil (2.54 mm).

Terminations

Proper termination of transmission lines is necessary to prevent reflections. Some common termination schemes are:

• Series termination at the driver
• Parallel termination at the receiver
• AC termination (series RC)
• Differential termination (100-120 Ω across differential pair)

The best termination depends on the topology (point-to-point vs multi-drop) and impedance requirements.

Crosstalk Reduction

Crosstalk is unwanted coupling between signals on adjacent traces. It becomes a bigger problem at high frequencies and with long parallel trace runs. To minimize crosstalk:

Increase spacing

The further apart traces are, the less they will couple. Use at least 3x the trace width for spacing when possible.

Minimize parallel run length

The longer two traces run parallel, the more they will couple. Try to minimize long parallel segments, or interleave non-switching signals between aggressors if needed.

Add shielding

For sensitive signals, adding ground traces or planes adjacent to the signal can provide shielding. Differential pairs are inherently resistant to crosstalk.

Route on different layers

Separating troublesome nets on different layers with a power or ground plane in between provides excellent isolation.

Power Integrity and Decoupling

Maintaining a low impedance power distribution network (PDN) is critical for power integrity. As logic switches, the sudden current draws can cause supply rail collapse, ground bounce, and increased EMI if not properly managed.

Power plane

Use uninterrupted power and ground planes whenever possible. This provides the lowest impedance and inductance for current flow.

Local decoupling

Place decoupling capacitors as close as possible to ICs. A combination of bulk, ceramic and small package caps is ideal to handle low, medium and high frequency current demands. Below is a typical decoupling scheme:

Capacitor	Value	Package
Bulk	22 uF	1206
Ceramic	0.1uF	0402
Small	100pF	0201

Minimize loop area

The path from IC to decoupling cap and back to IC should be as short as possible. Via placement is key to minimize loop area and inductance.

EMI Reduction

Electromagnetic interference (EMI) is the unintentional generation of radiated or conducted emissions from an electronic device. To pass EMC regulations and avoid interference issues, it’s important to design for low EMI from the start.

Keep loops small

Current loops are the primary source of unintentional radiated emissions. Keep signal loops, power loops and return paths short and close to the source to minimize loop area.

Filter at board edges

Place EMI filters close to connectors at the PCB boundary. Common mode chokes, ferrite beads and RC filters are effective at reducing high frequency noise on I/O.

Avoid stubs

Unterminated stubs can act like antennas to radiate noise. Eliminate stubs wherever possible, or keep them very short compared to wavelength.

Add shielding

For very sensitive designs, a metal shield over noisy components may be added. Stitching vias around the shield perimeter at <λ/20 spacing provides a good Faraday cage.

Layer Stack Considerations

The PCB layer stack is the arrangement of signal, power and dielectric layers that make up the board. A well designed stack enables good SI and PI performance.

Signal layers

Ideally, critical signals should be routed on layers adjacent to uninterrupted reference planes. Stripline routing between planes provides the best SI.

Power/Ground planes

Use at least one set of closely spaced power and ground planes, with a thin, high Er dielectric for low impedance. Multiple plane sets provide better isolation for analog/digital supplies.

Symmetric stack

A symmetric stack ensures the PCB will be flat after fabrication. Otherwise, uneven copper balance and shrinkage can cause warpage.

A typical 6 layer high speed stack up is:

Layer	Function
1	Signal
2	GND plane
3	Signal
4	Power plane
5	Signal
6	Signal

Layout Topology Optimization

With the SI, PI and EMI considerations in mind, let’s look at some specific optimizations for common high speed layout topologies.

Star Topology

A star topology has a central node with point-to-point connections fanning out to peripherals. This is common for clock distribution.

• Keep all trace lengths equal from center to endpoints
• Use a symmetric star for best length matching
• Place series termination resistors at the star center
• Avoid daisy-chaining loads off endpoints

Multi-Drop Bus

A multi-drop bus has several loads connected to a common set of parallel traces, like a DRAM bus.

• Keep stubs as short as possible
• Place loads near the center, not ends of bus
• Terminate far end of bus if not used
• Consider fly-by routing instead of T-taps for fast signals

Daisy Chain

Components are connected in a linear chain, like for a JTAG boundary scan.

• Length match traces between devices
• Place AC terminations at each device
• Avoid stubs at the endpoints
• Route entire chain on one layer if possible

FAQ

What is the most important factor for high speed PCB layout?

Maintaining consistent trace impedance is one of the most critical aspects of high speed PCB design. Impedance discontinuities lead to reflections, ringing and SI issues.

How do you control trace impedance?

The main factors that determine trace impedance are:

• Trace width and thickness
• Dielectric height between trace and reference plane
• Dielectric constant (Er) of the PCB material

These parameters must be tightly controlled and modeled with a field solver to achieve target impedance.

What is the best way to decouple ICs?

Effective decoupling requires multiple capacitor values placed very close to the IC supply pins. Use a combination of small package (0201) 100pF, larger (0402) 0.1uF and bulk (1206) 1-10uF caps to handle low, medium and high frequency transients. The loop area from cap to IC and back must be minimized.

How can you reduce crosstalk between signals?

Some ways to reduce crosstalk are:

• Increase spacing between signal traces (3W rule)
• Minimize long parallel trace segments
• Route sensitive signals on different layers
• Add ground guard traces or planes for shielding
• Use tightly coupled differential pairs

What is the best layer stack for high speed design?

The optimal layer stack depends on the design, but in general a high speed stack should have:

• At least one set of closely spaced power/GND planes
• Critical signals routed on layers adjacent to reference planes
• Multiple plane sets for isolation of analog/digital supplies
• Symmetric copper balance to prevent warpage

With attention to SI, PI, EMI and a carefully planned layer stack and topology, you can design reliable and robust high speed PCBs. As always, simulating and verifying your design before fabrication is highly recommended.